This invention relates to the formation of backend-of-line (BEOL) interconnect structures in integrated circuits. More particularly, this invention relates to new damascene interconnect structures including etchback for low-k dielectric materials, and new methods of forming these interconnect structures.
The semiconductor industry roadmap calls for lowering the dielectric constant on the insulation surrounding multi-level on-chip interconnects. The dielectric constant must be lowered so as to reduce the parasitic capacitive load to the integrated circuits, as well as to reduce the capacitive coupling between neighboring interconnects.
Reducing dielectric constant often comes with a concomitant reduction in insulator mechanical properties such as modulus, hardness, thermal conductivity and fracture toughness. Significant stresses can develop in the structure due to thermal expansion mismatches with the substrate and the metal interconnects. These stresses can cause fatigue of copper vias or studs during thermal cycling, resulting in yield or reliability problems. A method is therefore needed to provide the strength characteristics of dielectric materials having higher dielectric constant immediately adjacent to copper vias or studs, while providing dielectric materials having lower dielectric constant in other areas of the interconnect level.
U.S. Pat. No. 6,331,481 to Stamper et al., the disclosure of which is incorporated herein by reference, discloses a method of integrating a low dielectric material into a dual or single damascene wiring structure which contains a dielectric material having a higher dielectric constant. This integration is achieved by employing the step of etching back the higher dielectric constant material to expose regions of in-laid wiring present in the damascene structure. The Stamper et al. method is shown in FIGS. 5(a)-5(e), which correspond to FIGS. 1(A)-1(E) in the Stamper et al. patent. The method begins with a typical dual damascene structure such as that shown in FIG. 5(a), including dielectric 52 and in-laid wiring 54. This damascene structure is then etched back so as to expose regions of in-laid wiring 54, as shown in FIG. 5(b). A polish stop layer 56 is then optionally deposited over the exposed regions of the structure, as shown in FIG. 5(c). Finally, a second dielectric material 58 is deposited onto the etchback structure or polish stop layer 56, and is then planarized, as shown in FIGS. 5(d)-5(e). The second dielectric material 58 has a dielectric constant lower than the first dielectric material 52, thereby lowering the overall dielectric constant of the interconnect level.
The method and resulting structure of the Stamper et al. patent has the following drawbacks. First, the copper wiring 54 is exposed during the etchback, which could result in erosion. Second, the copper may undergo silicidization during exposure to the etchback process, resulting in higher resistivity. Finally, exposing the sidewalls of the copper wiring 54 during etchback of the first dielectric material 52 may result in loss of wire sidewall mechanical support, which may cause the wire to “flop over” or may cause other mechanical integrity issues. Deposition of the optional polish stop layer 56 protects the copper wiring 54 from erosion or silicidization during etchback, but does not address the mechanical integrity issues. Moreover, deposition of this polish stop layer 56 is a costly additional step in the process.
Therefore, there remains a need in the art for a method of forming a damascene interconnect structure utilizing etchback and deposition of a second, lower dielectric constant material, but which does not suffer from the drawbacks of the prior art.